1. Technical Field
The present invention relates to a switching power supply unit that performs a voltage conversion by carrying out a switching in accordance with a pulse width modulation signal (hereafter called a PWM signal), and in particular, relates to a digital control switching power supply unit having an analog-to-digital converter circuit (hereafter called an A/D converter circuit) preferable for control using a digital signal.
2. Related Art
FIG. 12 shows a first configuration example of a heretofore known common digital control switching power supply unit. The digital control switching power supply unit shown in FIG. 12, being a configuration example of a digital control switching power supply unit of a voltage mode wherein a switching element is controlled by a PWM signal and an input voltage Vin is converted to an output voltage Vout, is configured of a subtraction circuit Sub, an A/D converter circuit 12, a digital compensation circuit 22, a digital PWM circuit 32, a switching circuit 41 including a drive circuit DRV and a P-channel MOSFET (hereafter called a PMOS) Q1 and N-channel MOSFET (hereafter called an NMOS) Q2, which are a pair of switching elements controlled by the drive circuit DRV, and an LC smoothing filter 51 including an inductor L and a capacitor C. Also, Vin is a power supply that inputs an input voltage Vin into the digital control switching power supply unit (a power supply and its voltage are given the same reference numerals and characters), and RL is a load circuit.
In the configuration of FIG. 12, a detected value of the output voltage Vout (the output voltage itself, the output voltage divided, the output voltage level shifted, or the like) is fed back, and an error voltage Ve ((Vref−Vout), (Vref−K1·Vout), (Vref−(Vout−K2)), or the like, where K1 and K2 are positive constants) between the detected value and a reference value Vref, which is a target value, is generated by the subtraction circuit Sub. The error voltage Ve is sampled in the A/D converter circuit 12 for each switching cycle Ts, and converted into a digital error signal e(n) (herein, (n) indicates that it is a signal in an nth switching cycle). The digital compensation circuit 22 performs a proportional integral and differential (PID) process on the input digital error signal e(n), and calculates a duty command signal dc(n) that controls the duty of the PWM signal. The digital PWM circuit 32 generates the PWM signal based on the calculated duty command signal dc(n). The switching circuit 41 on-off controls the switching elements Q1 and Q2 in accordance with the PWM signal, and the LC smoothing filter 51 smoothes an output of the switching circuit 41, generates the output voltage Vout, and supplies it to the load circuit RL.
Herein, as only a small number of bits are necessary in order to express a conversion range or conversion result of the A/D converter circuit in the case of the specifications of the common switching power supply unit, a delay line A/D converter (ADC), which utilizes an element delay time that changes depending on an operating voltage or operating current, is used in the digital control switching power supply unit (for example, refer to JP-T-2005-512493).
FIG. 13 shows a configuration example of a heretofore known delay line ADC. The delay line ADC is configured of a delay time adjusting delay element dmy, a delay element array d1 to d(n) configured of n stages of delay elements Dcell connected in series, n flip-flops DFF that store an output of each delay element Dcell at a rising edge of a data storage signal Sample, and an encoder circuit 5 that generates the digital error signal e(n) from an output of the n flip-flops DFF.
In FIG. 13, the delay element dmy is inserted with the object of adjusting the overall delay time, in order to optimize the delay time of the delay element array d1 to d(n). Also, a control signal Dcont is a signal for controlling the delay times of the delay element dmy and the delay elements Dcell.
FIGS. 14A and 14B show a timing chart of the delay line ADC shown in FIG. 13. The delay line ADC carries out an A/D conversion operation for each switching cycle Ts (a cycle of a switching clock CLK-SW, which is a basic clock) of the switching power supply unit. The A/D conversion operation starts at the rise of an A/D conversion start signal Start synchronized with the switching clock CLK-SW, and is reset and finished at the decay of the signal.
FIG. 14A shows a timing chart in the case of a normal frequency. On the A/D conversion start signal Start being input into the delay element dmy, that is, on the input of the delay element dmy changing to an H (high) level, the H level is delayed by a delay time tdd by the delay element dmy, transmitted to the delay element d1 at the first stage of the delay element array, then transmitted sequentially through the delay element array d1 to d(n) while being delayed in each delay element by a constant delay time td. Outputs d1 to d(n) (an element and its output are given the same reference numerals and characters) of the delay elements Dcell are stored in the n flip-flops DFF at the rise of the data storage signal Sample, whose timing is set in advance. Then, by output data out1 to out(n) of the n flip-flops DFF representing the stored d1 to d(n) being encoded by the encoder circuit 5, the digital error signal e(n) is obtained. Herein, the data out1 to out(n) are such that the first k items of data out1 to out(k) are H level, while the remaining items of data out(k+1) to out(n) are L (low) level signals. Then, when the value of the control signal Dcont is such as to lengthen the delay times of the delay element dmy and delay elements Dcell, the number of delay elements through which the H level is transmitted decreases, meaning that the value of k decreases, while when the value of the control signal Dcont is such as to shorten the delay times, the number of delay elements through which the H level is transmitted increases, meaning that the value of k increases. In this way, the delay line ADC realizes the A/D conversion in accordance with the control signal Dcont by controlling the storage timing with the delay times tdd and td and the data storage signal Sample.
Then, the total time of the A/D conversion time and digital compensation circuit 22 duty command signal dc(n) calculation time has to be set so as to be equal to or shorter than the switching cycle Ts (operating times of the subtraction circuit Sub and digital PWM circuit 31 can be ignored).
For this reason, in order to reliably complete the A/D conversion and duty command signal dc(n) calculation within the switching cycle Ts, even in the event of a variation in the switching cycle Ts or delay time occurring due to the effect of a process fluctuation or a variation in element size, it is necessary to secure a temporal margin.
Furthermore, in a case of making the switching frequency variable, and the frequency settable on a user side, it is necessary to set in such a way that the A/D conversion and duty command signal dc(n) calculation are completed within a minimum switching cycle stipulated by the specifications. FIG. 14B shows a timing chart wherein the A/D conversion and duty command signal calculation are possible at a switching frequency up to two times higher, but the necessary margin is extremely large.
With the digital control switching power supply unit, as a digital signal processing such as a PID calculation is necessary, a feedback control takes longer than with an analog control method, and it is known that there is a problem with transient response characteristics. When applying this delay line ADC to a switching power supply unit, it is necessary to secure a temporal margin as heretofore described, and the delay time further increases. As the temporal margin is the delay time until an A/D conversion result is reflected in the PWM signal, the kind of excessive margin time shown in FIG. 14B delays feedback to the output of an A/D conversion result, and the transient response characteristics of the switching power supply unit are worsened considerably.
As a digital control switching power supply unit that improves the transient response characteristics, a circuit structure wherein a transient fluctuation detector circuit for a time of sudden load change is newly provided in addition to the normal digital signal processing circuit, and an output voltage is controlled without going through a digital signal processing at a time of sudden load change, is introduced in JP-A-2008-113542.
FIG. 15 shows a circuit configuration of the digital control switching power supply unit described in JP-A-2008-113542 as a second configuration example of a heretofore known digital control switching power supply unit. The same reference numerals and characters are given to places which are the same as in the first configuration example of a heretofore known digital control switching power supply unit shown in FIG. 12, and a detailed description will be omitted.
The digital control switching power supply unit shown in FIG. 15 is configured of a digital signal processing circuit portion 61, the switching circuit 41, the LC smoothing filter 51, a transient fluctuation detector circuit 71 including two comparators CP1 and CP2, and a CR filter 81 including a resistor R2 and a capacitor C2.
The digital signal processing circuit portion 61 is configured of an A/D converter circuit 13, a digital voltage control circuit 23, a digital PWM circuit 33, a Vref±Δ circuit 62 that outputs voltages of reference voltages Vref+Δ and Vref−Δ, and an SEL circuit 63 that selects and outputs a PWM signal at a normal time or at a time of a sudden load change.
At a time of a normal operation (Vref+Δ>Vout>Vref−Δ), a digital signal processing is carried out in the A/D converter circuit 13, digital voltage control circuit 23, and digital PWM circuit 33, and a PWM signal, which is an output of the digital PWM circuit 33, is selected and output to the switching circuit 41 via the SEL circuit 63. That is, the same kind of switching control operation as in the heretofore known first configuration example shown in FIG. 12 is carried out.
Meanwhile, an operation at a time of a sudden load change is such that a sudden load change voltage VoCR detected by the CR filter 81, and the voltages Vref±A which are references, are compared by the comparators CP1 and CP2 of the transient fluctuation detector circuit 71, and a drive control method of the switching circuit 41 is selected.
Firstly, in the case of a time of a sudden load reduction (Vout>Vref+Δ), the SEL circuit 63 is controlled by a detection signal α0 of the comparator CP1, and a 0% duty PWM signal is selected and output, thus driving the switching circuit 41. Next, in the case of a time of a sudden load increase (Vout<Vref−Δ), the SEL circuit 63 is controlled by a detection signal α100 of the comparator CP2, and a 100% duty PWM signal is selected and output, thus driving the switching circuit 41. By means of the heretofore described operations, the transient response characteristics of the output voltage Vout at a time of a sudden load change are improved.
The following kinds of problem exist with the heretofore described heretofore known digital control switching power supply units.
Firstly, with the heretofore known first configuration example shown in FIG. 12, there is a problem in that a temporal margin is needed in the A/D conversion cycle, and there occurs a delay time until the PWM signal is generated based on the digital error signal e(n), wherein the error voltage between the output voltage Vout and reference voltage Vref is A/D converted by the delay line ADC, and the output voltage Vout is controlled, and the transient response characteristics of the output worsen. In order to improve the transient response characteristics, a quickening of the switching cycle Ts is also conceivable, but a problem also occurs in that a quickening of the elements used is also inevitably required, expensive elements become necessary, and the current consumed increases along with the quickening.
Also, with the heretofore known second configuration example shown in FIG. 15, a quickening of the transient response characteristics is realized by providing the transient fluctuation detector circuit 71, the CR filter 81, and the like, separate from the normal digital signal processing circuit, and controlling with a 0% or 100% duty PWM signal at a time of a sudden load change of the output voltage Vout. However, there is a problem in that a dedicated detector circuit or circuit parts are newly necessary at a time of a sudden load change, and the circuit scale becomes enormous. Also, there is a problem in that signal controls of an operation at a normal time and an operation at a time of a sudden load change become complicated, and furthermore, it is necessary to individually set a sudden load change detection voltage and the voltage range Vref±A, which forms a reference, in accordance with the specifications of the switching power supply unit.